This invention relates to frequency synthesizers and more particularly to a phase locked loop (PLL) frequency synthesizer having a multiple order loop filter with a parameter tolerant placement of symmetric ratio.
PLL synthesizers are widely used in various communications systems to provide accurate frequency control of signal oscillators. This control is not perfect in that a finite time is required to synthesize a frequency to a given accuracy limit. In addition, a trade-off exists between the speed of phase lock acquisition and spurious noise performance of the synthesizer.
In previous communications systems, the phase lock time was less demanding than presently required in the new digital cellular systems. Digital radio systems must be locked to within a specified frequency within a critical time interval or the data conveyed by the system will be un-recoverable. In addition, subscriber units, which move about the radio coverage areas of the system, are continually checking the channels available in a coverage adjacent to the coverage area providing communication service and are frequency hopping in the service-providing coverage area. Therefore, the frequency locking process occurs continually during the time a communication channel is in use between the subscriber unit and a fixed station in the service providing coverage area. Therefore, the lock time must be maintained below stringent limits.
Current PLL synthesizer designs use third order PLLs in which there is one "mobile" pole and one "mobile" zero in the transfer function of the open loop response. The pole frequency and zero frequency are selected to be geometrically symmetric about the open loop unity gain frequency. The ratio of the open loop unity gain frequency to the zero frequency is therefore called the symmetric ratio.
A third order PLL is shown in FIG. 1 and has an equation for the open loop conventionally written as follows: ##EQU1##
N=frequency division ratio of divider 111 and ##EQU2##
Plots of the gain and phase of this expression are presented in FIG. 2. These plots are used to analyze system stability such that when the gain crosses 0 db the phase will not be less than -180.degree.. This is a familiar condition for stability. The degree of stability is measured by the difference in phase from -180.degree. at the frequency where the gain is unity. This frequency is called w.sub.o and is the open loop unity gain frequency. The phase in excess of -180.degree. at this point is known as the phase margin.
At low frequencies there are two inherent poles, one from the VCO 103 frequency-to-phase conversion, and one from the current sources 105 and 107 at the output of the phase detector 109 driving a capacitor (C.sub.2) input filter. As shown in FIG. 2, this configuration results in a frequency response curve slope of -12 db/octave. When the frequency crosses w.sub.z then the slope breaks to one net pole or -6 db/octave. Finally when the frequency crosses w.sub.p then the slope breaks again to two net poles or -12 db/octave and continues in this fashion as the frequency increases.
The phase response corresponding to this frequency response begins at -180.degree. at DC (0 Hz). As the zero is encountered, the phase increases and asymptotically approaches -90.degree.. Finally when the pole is encountered the phase decreases back to an asymptote of -180.degree.. Since the phase of the open loop never crosses -180.degree. this system is stable. Once the system stability has been established, the placement of the pole and zero may be selected such that the lock time is minimized for a given PLL bandwidth. It is more convenient to consider the open loop unity gain frequency instead of the closed loop PLL bandwidth. These frequencies will be nearly the same in practice.
A mathematical derivation is presented hereinafter which shows that the best possible lock time is achieved when the following condition is satisfied: ##EQU3##
This condition is known as symmetric pole placement about the open loop unity gain frequency. "X" is known as the symmetric ratio. The graph presented in FIG. 4 shows an example of lock time versus symmetric ratio for a fixed w.sub.o.
The derivation first assumes a symmetric pole-zero placement, then shows that this is the optimum condition with a symmetric ratio "X" of three, and then modifies this symmetric ratio slightly due to the damped sinusoidal nature of the locking waveform.
The open loop equation is: ##EQU4##
At the open loop unity gain frequency the magnitude of KG(s) must be one. ##EQU5##
Where X is the symmetric ratio, w.sub.o /w.sub.z =w.sub.p /w.sub.o =X, therefore: ##EQU6##
Factoring X.sup.2 out of the top radical then: ##EQU7##
Solving for w.sub.o : ##EQU8##
The function of interest is the frequency error of the loop. From conventional control theory this can be found as follows: ##EQU9##
where A(s) is the input function. ##EQU10##
Substituting in the expressions derived above for w.sub.o : ##EQU11##
Dividing numerator and denominator by w.sub.o and letting ##EQU12##
In general the inverse Laplace transform of the above equation results in three separate poles which will each exponentially decay with time. The fastest possible decay will occur if all three poles are at one frequency. (The lock time is dominated by the lowest frequency pole so if all are equal, no one pole dominates the response).
If X=3 then ##EQU13##
Thus, if a symmetric pole zero placement is chosen with X=3, it appears that the fastest possible lock time, given the loop bandwidth, will be obtained. But because the locking waveform is a damped sinusoid and X=3 represents the fastest locking envelope, it is possible to adjust the symmetric ratio slightly from that above and improve the lock time. The graph of the frequency error over time of FIG. 3 shows the situation.
From FIG. 3, it can be seen that the definition of initial frequency to what is an acceptable final error will determine what value of X is optimum, i.e., a different interpretation of "locked" may or may not catch the next peak of the damped sinusoid.
By simulating various symmetric ratios, it can be shown that X=3 or greater is an "overdamped" type of response. If the symmetric ratio is lower, then the loop rings such as an underdamped second order loop will ring. Use of this ringing allows the lock time to decrease even though the envelope of the lock time is greater.
When the excitation to the loop is a unit step in frequency, the lock time will be defined such that final lock corresponds to 4.times.10.sup.-7 times the initial step. ##EQU14##
Breaking into partial fractions: ##EQU15##
A standard form to obtain the inverse Laplace transform may be set up: ##EQU16##
Solving for the inverse transform from a table of standard forms yields: ##EQU17## where .tau.=.omega..sub.o t.
Thus, the fastest lock time to 4.times.10.sup.-7 of the initial step occurs for X=2.625. Other systems have required that a locked condition corresponded to 0.0001 times the initial step and in that case the fastest lock occurred for X=2.778. These derivations are valid for a continuous time model. If the loop bandwidth is more than 1% of the sampling frequency then a first order sampling corrected model should be used to find the best point.
Thus, it appears from the lock time versus symmetric ratio graph of FIG. 4 that the optimum symmetric ratio is X=2.7 for a third order loop. Present PLLs typically do indeed have the third order loop symmetric ratio selected in accordance with this criterion. This selection results in the fastest possible loop given the PLL bandwidth. However, since the components used to realize actual phase locked loops are subject to environmental extremes and normal part tolerance variation, the fastest loop selection is subject to variations in lock time which may result in undesired results.